1. Field of the Invention
The embodiments herein relate to a structure and method of manufacturing an embedded dynamic random access memory (eDRAM) cell array, in which each cell includes a field effect transistor (FET) formed on a silicon-on-insulator (SOI) substrate and a recessed trench capacitor that is self-aligned to a buried silicon strap. In particular, a passing wordline may be formed over a portion of a dielectric cap that covers the recessed trench capacitor of each eDRAM cell, thereby reducing the size of the eDRAM cell array. More particularly, the buried silicon strap may provide good electrical contact between a source/drain (S/D) region of the FET and the recessed trench capacitor.
2. Description of Related Art
A dynamic random access memory (DRAM) cell is essentially a capacitor for storing charge and an access transistor for transferring charge to and from the capacitor. One bit of data, determined by the presence or absence of charge on the capacitor, is stored in each DRAM cell.
A primary goal of designers is to increase chip density on a wafer of integrated circuit chips that include DRAM cell arrays. One way of increasing chip density is to reduce the size of DRAM cells within DRAM cell arrays by using trench capacitors, rather than planar capacitors. In a DRAM cell, a planar capacitor is used to store charge, in which the amount of charge stored is proportional to the area of the planar capacitor on the chip's surface. To increase chip density without sacrificing the amount of charge stored, deep trenches are etched in a silicon wafer to form trench capacitors, which are oriented vertically to with respect to the chip's surface. Thus, the surface area required for the capacitor is dramatically reduced without sacrificing capacitance and the amount of charge stored. The formation of multiple gate field effect transistors (MuGFETs) also allows for smaller DRAM cell sizes, while formation of planar FETs or MuGFETs on an SOI substrate improves transistor performance.
Referring to FIG. 1, a schematic diagram 100 illustrates a cross section of a portion of a row of a conventional eDRAM cell array that includes an eDRAM cell and a “passing wordline” 150 from an eDRAM cell in an adjacent row of the array. The eDRAM cell includes a trench capacitor 110 and, for example, a MuGFET access transistor 120, which is formed in the silicon layer 132 of an SOI substrate 130. Alternatively, a planar FET (not shown) may replace the MuGFET access transistor 120. A plate 112 of the trench capacitor 110 contacts a first source/drain (S/D) region 122 of the MuGFET 120 via a standard silicon strap 114, which covers the plate 112 of the trench capacitor 110. In the conventional method, the trench capacitor 110 must necessarily be formed before the overlying standard strap 114 is formed. The trench capacitor 110 extends from the plate 112 through the buried oxide (BOX) layer 134 and into the underlying substrate layer 136 of the SOI substrate 130 to a depth of several microns. A gate 128 of the MuGFET 120 covers a channel region and is disposed between a second S/D region 124 and the first S/D region 122. The “passing wordline” 150, from an eDRAM cell in an adjacent row of the eDRAM cell array, “passes” the eDRAM cell in a direction oriented perpendicularly to the page, and the trench capacitor 110 is separated from the passing wordline to prevent electrical coupling between the passing wordline 150 and the trench capacitor 110. The distance between the passing wordline 150 and the trench capacitor 110 adds to the area of the conventional eDRAM cell. A bit line contact 140 extends through an insulating layer 160 to contact the second S/D region of the MuGFET 120.
There remains a need for a structure and a method of manufacturing a smaller FET eDRAM array, including trench capacitors, to further increase chip density, improve performance, and reduce cost.